The computer industry has established an interface protocol for computer systems, the Low Pin Count (LPC) Interface, specifically to facilitate the industry's transition toward eliminating ISA buses and protocols (e.g., see Intel Low Pin Count (LPC) Interface specification, Aug. 2002, Revision 1.1, Document Number 251289-001). The LPC Interface Specification describes memory, I/O, and DMA transactions and allows legacy I/O motherboard components to migrate from the ISA/X-bus to the LPC Interface and to synchronize system function with a PCI clock to increase performance. The LPC interface offers several advantages over the ISA/X-bus, such as reduced pin count for easier, more cost-effective designs, using less space and power, and improved thermal efficiency. The LPC Interface Specification is software transparent for I/O functions and compatible with existing peripheral devices and applications.
The LPC specification allows system and peripheral suppliers to migrate from ISA/X-bus to future systems not employing an ISA bus while retaining full software compatibility. This allows manufacturers to reduce overall design costs and facilitates the industry's move toward new generation input/output or communication devices. An example of a new generation input/output device is an LPC-based Super I/O device which integrates multiple functions into a single chip, providing cost and board space savings, and incorporating I/O technologies such as USB and 1394 (firewire). Manufacturers also provide general-purpose LPC compatible microcomputers that integrate the functions of conventional 8-bit processors into smaller (low-pin-count) packages having peripheral functions, for example, an on-chip serial interface for synchronous or asynchronous communication, timers, and A/D converters to enable analog signal input into digital-signal processors useful for the control of home electric appliances and office automation equipment. LPC compatible flash memories may interface with non-Intel chipsets via the LPC interface.
The LPC interface specification includes a physical connection of 7 lines, containing 4 lines (LAD) that are used to multiplex commands, addresses, and data, a line for a frame bit signal (LFRAME), a line for a reset signal (LRESET), and a clock line (LCLK). Configuration hosts (CPU) and peripheral devices are both required to minimally implement these signals. An additional 6 signals are optional, expanding the interoperability of the LPC interface.
Referring to FIG. 1, a prior art computer system 100 is typically configured using a processor (CPU) 110 and a core-logic chipset 120, for example, containing north bridge (NB) 121 and south bridge (SB) 122 architecture circuits. The north bridge 121 typically serves as the logic connecting a CPU 110 to a bus such as an ISA bus or a PCI bus, memory (not shown), a video card (AGP) bus (not shown), and the south bridge 122. The south bridge handles most of the input/output or data communications functions of the computer system 100, such as an IDE controller, USB controller or 1394 firewire, onboard sound or audio, an Ethernet or LAN port, modem or wireless access point, DMA functions, interrupts, and power control (all shown as 160). The south bridge also 122 allows input/output (I/O) devices, such as a Super I/O device 140 or generic controller 150, to communicate with the CPU 110 and memory (not shown) via an LPC interface. In addition, the LPC compatible flash memory (bios) 130 may be designed to store system and graphics BIOS code.
The LPC I/O map contains 216 (65,536) configuration addresses locations. However, only a few of these configuration address are typically mapped by the south bridge 122 and a typical computer system 100 (e.g., a motherboard) will designate or support a limited number of unreserved LPC configuration addresses. Having a limited number of configuration address locations may pose a problem, because a bus contention problem occurs when multiple devices are assigned the same address and both devices respond when being addressed. Therefore, each LPC device is forced to have a unique address in order to properly operate in an LPC interface environment.
Information relevant to address this type of problem may be found in U.S. Pat. No. 5,588,122 to Garcia, entitled “Universal Buffered Interface for Coupling Multiple Processors Memory Units, and I/O Interfaces to a Common High-Speed Interconnect” which describes coupling a local bus to a global bus and supporting up to four local nodes. However, the interface only allows interrupts during a specially marked bus cycle. U.S. Patent Publication No. 2003/0046462 to Wolf et al. entitled “Methods and Apparatus for Pipelined Bus” describes an interface to computing elements that supports multiple non-interfering transfers concurrently on a bus. However, in Wolf et al., clients are assigned unique identification numbers based upon a mapping from the system address space. Each of these references suffers from a disadvantage of not addressing the problem of multiple devices that have or are assigned the same (configuration) address.